Design verification Engineer

Negotiable

San Diego, CA, United States

10 months ago

Role: Design verification Engineer Location: San Diego, CA (Onsite from day one) Duration: Full Time/Contract Day 1 onsite • Problem Solving skills / methodical & analytical debugging skills • System Verilog / Object Oriented programming • System Verilog constrained randomization • System Verilog coverage • Test planning • SOC • Simulation • Nice-to-have: power management / low power / upf • UVM (sequence writing, component building) • Failing regression triage and debugging / UVM environment debugging / testcase debugging • Coverage closure -- analyzing holes, building testcases, building exclusions/refinements • Team focused / energetic person • Nice-to-have: knowledge of git / continuous integration / code review process\

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Negotiable

Company

Hyderabad, India

1-10 employees

Founded: 2010