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Kalpana senthamarai kannan

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Intro
Einthoven, Netherlands
Nanotechnology
Joined March 15, 2021

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English
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Fluent
French
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Basic
Dutch
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Basic
Tamil
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About
FPGA/ASIC Design Engineer with experience in RTL Design, Synthesis, Implementation engineer, and Timing analysis
Experience
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TIMA Laboratory
Nov 2017 – Mar 2021
France
Ph.D Student
• Development of safety monitors for detection of process, voltage, and aging variation for IoT applications. • Design of methodology to embed safety monitors in the digital design. • Design and Implementation of IPs in 28nm FDSOI technology to verify the functionality of safety monitors on Silicon: RTL wrappers, RTL and back-annotated simulation, STA, Physical design, Signoff, Physical verification, Transistor level fast-spice simulation • Machine Learning Algorithm along with adaptive compensation scheme for PVTA variations