FPGA/ASIC Design Engineer with experience in RTL Design, Synthesis, Implementation engineer, and Timing analysis
Experience
TIMA Laboratory
Nov 2017 – Mar 2021
France
Ph.D Student
• Development of safety monitors for detection of process, voltage, and aging variation for IoT applications.
• Design of methodology to embed safety monitors in the digital design.
• Design and Implementation of IPs in 28nm FDSOI technology to verify the functionality of safety monitors on Silicon: RTL wrappers, RTL and back-annotated simulation, STA, Physical design, Signoff, Physical verification, Transistor level fast-spice simulation
• Machine Learning Algorithm along with adaptive compensation scheme for PVTA variations
